3.6.6. Abort

An abort indicates that the current memory access cannot be completed. It can be signalled either by the Protection unit, or by the external BERROR input. ARM720T checks for the abort exception during memory access cycles.

There are two types of abort:

Prefetch abort

occurs during an instruction prefetch.

Data abort

occurs during a data access.

If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception is not taken until the instruction reaches the head of the pipeline. If the instruction is not executed—for example because a branch occurs while it is in the pipeline—the abort does not take place.

If a data abort occurs, the action taken depends on the instruction type:

  1. Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be aware of this.

  2. The swap instruction (SWP) is aborted as though it had not been executed.

  3. Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the instruction would have overwritten the base with data (that is, it has the base in the transfer list), the overwriting is prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last register to be transferred) is preserved in an aborted LDM instruction.

After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or THUMB):

SUBS PC, R14_abt, #4    for a prefetch abort, or

SUBS PC, R14_abt, #8    for a data abort

This restores both the PC and the CPSR, and retries the aborted instruction.


There are restrictions on the use of the external abort signal. See External Aborts.

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