3.6.9. Exception vectors

The ARM720T can have exception vectors mapped to either low or high addresses, controlled by the V bit in the Control Register (Register 1: Control register). The following table shows the exception vector addresses.

Table 3.4. Exception vector addresses

High Address Low Address ExceptionMode on entry
0xFFFF0000x00000000 Reset Supervisor
0xFFFF0040x00000004 Undefined instructionUndefined
0xFFFF0080x00000008 Software interruptSupervisor
0xFFFF00C0x0000000C Abort (prefetch)Abort
0xFFFF00100x00000010 Abort (data)Abort
0xFFFF00140x00000014ReservedReserved
0xFFFF00180x00000018 IRQIRQ
0xFFFF01C0x0000001C FIQ FIQ

Note

Note that the low addresses are those generated by the processor core before the relocation by the Process ID.

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