4.1.1. Compatibility

To ensure backwards compatibility of future CPUs:

  1. All reserved or unused bits in registers and coprocessor instructions should be programmed to “0”.

  2. Invalid registers must not be read/written.

  3. The following bits must be programmed to “0”:

    Register 1

    bits[31:14] and bits [12:10]

    Register 2

    bits[13:0]

    Register 5

    bits[31:9]

    Register 7

    bits[31:0]

    Register 13

    bits[24:0]

Note

The gray areas in the register and translation diagrams are reserved and should be programmed 0 for future compatibility.

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