4.3.6. Register 5: Fault Status Register

Reading CP15 register 5 returns the value of the Fault Status Register (FSR). The FSR contains the source of the last data fault.

Note

Only the bottom 9 bits are returned. The upper 23 bits are unpredictable.

The FSR indicates the domain and type of access being attempted when an abort occurred:

Bit 8

is always read as zero. Bit 8 is ignored on writes.

Bits [7:4]

specify which of the sixteen domains (D15-D0) was being accessed when a fault occurred.

Bits [3:1]

indicate the type of access being attempted.

The encoding of these bits is shown in Fault Address and Fault Status Registers (FAR & FSR). The FSR is only updated for data faults, not for prefetch faults.

Writing CP15 register 5 sets the Fault Status Register to the value of the data written. This is useful when a debugger needs to restore the value of the FSR. The upper 24 bits written should be zero.

The CRm and opcode_2 fields should be zero when reading or writing CP15 register 5.

Figure 4.9. Register 5

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E
Non-Confidential