4.3.8. Register 7: Cache Operations

Writing to CP15 register 7 manages the ARM720T’s unified instruction and data cache. Only one cache operation is defined using the following opcode_2 and CRm fields in the MCR instruction that writes the CP15 register 7:

Table 4.2. Cache operation

Functionopcode_2 valueCRm valueDataInstruction
Invalidate ID cache0b0000b0111SBZMCR p15, 0, Rd, c7, c7, 0

Reading from CP15 register 7 is undefined.

The “Invalidate ID cache” function invalidates all cache data. Use with caution.

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