4.3.9. Register 8: TLB Operations

Writing to CP15 register 8 is used to control the Translation Lookaside Buffer (TLB). The ARM720T implements a unified instruction and data TLB.

Two TLB operations are defined, and the function to be performed selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 8.

Table 4.3. TLB operations

Functionopcode_2 valueCRm valueDataInstruction
Invalidate TLB0b0000b0111SBZMCR p15, 0, Rd, c8, c7, 0
Invalidate TLB single entry0b0010b0111Virtual AddressMCR p15, 0, Rd, c8, c7, 1

Reading from CP15 register 8 is undefined.

The “Invalidate TLB” function invalidates all of the unlocked entries in the TLB.

The “Invalidate TLB single entry” function invalidates any TLB entry corresponding to the Virtual Address given in Rd.

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