5.1.1. IDC operation

ARM720T contains an 8KB mixed instruction and data cache (IDC).

The C bit in the ARM720T Control Register and the Cacheablebitin the MMU page tables only affect loading data into the Cache. The Cache is always searched regardless of these two bits. If the data is found then it is used, so when the cache is disabled, it should also be flushed.

The IDC has 512 lines of 16 bytes (four words), arranged as a 4‑way set‑associative cache, and uses the virtual addresses generated by the processor core after relocation by the Process Identifier as appropriate. The IDC is always reloaded a line at a time (4 words). It may be enabled or disabled via the ARM720T Control Register and is disabled on BnRES.

The operation of the cache is further controlled by the Cacheable (C bit) stored in the Memory Management Page Table—see Chapter 7 Memory Management Unit (MMU). For this reason, the MMU must be enabled in order to use the IDC. However, the two functions may be enabled simultaneously, with a single write to the Control Register.

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