5.1.2. Cacheable bit

The Cacheable bit determines whether data being read may be placed in the IDC and used for subsequent read operations. Typically, main memory is marked as cacheable to improve system performance, and I/O space as non-cacheable to stop the data being stored in ARM720T's cache.

For example, if the processor is polling a hardware flag in I/O space, it is important that the processor is forced to read data from the external peripheral, and not a copy of the initial data held in the cache. The Cacheable bit can be configured for both pages and sections.

Cacheable reads (C = 1)

A linefetch of four words is performed when a cache miss occurs in a cacheable area of memory, and it is randomly placed in a cache bank.

Uncacheable reads (C = 0)

An external memory access is performed and the cache is not written.

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