7.3.1. Translation table base

The translation process is initiated when the on-chip TLB does not contain an entry for the requested virtual address. The Translation Table Base (TTB) Register points to the base of a table in physical memory which contains Section and/or Page descriptors.

The 14 low-order bits of the TTB Register are set to zero as illustrated in Figure 7.1.

Figure 7.1. Translation table base register

Note

That the table must reside on a 16KB boundary.

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