7.14.1. Alignment fault

If Alignment Fault is enabled (bit 1 in Control Register set), the MMU generates an Alignment Fault on any data word access without a word-aligned address, irrespective of whether the MMU is enabled or not. In other words, if either of virtual address bits [1:0] are not 0, the Alignment Fault is enabled.

An Alignment Fault is not generated on any instruction fetch, nor on any byte access.

Note

If the access generates an alignment fault, the access sequence abort without reference to further permission checks.

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