8.3.2. Entering debug state on watchpoint

Watchpoints occur on data accesses. A watchpoint is always taken, but the core may not enter debug state immediately. In all cases, the current instruction does complete. If this is a multi-word load or store (LDM or STM), many cycles may elapse before the watchpoint is taken.

Watchpoints can be thought of as being similar to data aborts. The difference is that if a data abort occurs, although the instruction completes, all subsequent changes to ARM7DMT’s state are prevented. This allows the cause of the abort to be cured by the abort handler, and the instruction re-executed. In the case of a watchpoint, the instruction completes and all changes to the core’s state occur (load data is written into the destination registers, and base writeback occurs). Thus, the instruction does not need to be restarted.

Watchpoints are always taken. If an exception is pending when a watchpoint occurs, the core enters debug state in the mode of that exception.

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