8.4.1. Scan limitations

The three scan paths are referred to as scan chain 0, 1 and 2: these are shown in Figure 8.2.

Scan chain 0

allows access to the entire periphery of the ARM7DMT core, including the data bus. The scan chain functions allow inter‑device testing (EXTEST) and serial testing of the core (INTEST). The order of the scan chain (from SDIN to SDOUTMS) is:

  • data bus bits 0 through 3

  • the control signals

  • the address bus bits 31 through 0

Scan chain 1

is a subset of the signals that are accessible through scan chain 0. Access to the core’s data bus D[31:0], and the BREAKPT signal is available serially. There are 33 bits in this scan chain; the order is (from serial data in to out):

  • data bus bits 0 through 31

  • BREAKPT

Scan Chain 2

allows access to the EmbeddedICE registers. See Chapter 9 EmbeddedICE Macrocell for details.

Scan Chain 15

allows access to the System Control Coprocessor registers.

Figure 8.2. ARM7DMT scan chain arrangement

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