8.7.1. Bypass register

This register bypasses the device during scan testing by providing a path between TDI and TDO. The bypass register is 1 bit in length.

Operating mode

When the BYPASS instruction is the current instruction in the instruction register, serial data is transferred from TDI to TDO in the SHIFT-DR state with a delay of one TCK cycle.

There is no parallel output from the bypass register.

A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE-DR state.

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