8.7.4. Scan chain select register

This register changes the current active scan chain. The register is 4 bits in length.

Operating mode

After SCAN_N has been selected as the current instruction, when in the SHIFT-DR state, the Scan Chain Select Register is selected as the serial path between TDI and TDO.

During the CAPTURE-DR state, the value 1000 binary is loaded into this register. This is shifted out during SHIFT-DR (lsb first), while a new value is shifted in (lsb first).

During the UPDATE-DR state, the value in the register selects a scan chain to become the currently active scan chain. All further instructions, such as INTEST, then apply to that scan chain.

The currently selected scan chain only changes when a SCAN_N instruction is executed, or a reset occurs. On reset, scan chain 3 is selected as the active scan chain.

The number of the currently selected scan chain is reflected on the SCREG[3:0] outputs. The TAP controller may be used to drive external scan chains in addition to those within the ARM7DMT macrocell. The external scan chain must be assigned a number and control signals for it can be derived from SCREG[3:0], IR[3:0], TAPSM[3:0], TCK1 and TCK2.

The list of scan chain numbers allocated by ARM are shown in Table 8.1. An external scan chain may take any other number. The serial data stream to be applied to the external scan chain is made present on SDINBS, the serial data back from the scan chain must be presented to the TAP controller on the SDOUTBS input.

The scan chain present between SDINBS and SDOUTBS will be connected between TDI and TDO whenever scan chain 3 is selected, or when any of the unassigned scan chain numbers is selected. If there is more than one external scan chain, a multiplexer must be built externally to apply the desired scan chain output to SDOUTBS. The multiplexer can be controlled by decoding SCREG[3:0].

Table 8.1. Scan chain number allocation

Scan Chain NumberFunction
0Macrocell scan test
1Debug
2EmbeddedICE programming
3External boundary scan
4Reserved
8Reserved
15System Control Coprocessor
Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E
Non-Confidential