8.7.5. Overview of scan chains 0,1, 2 and 15

These allow serial access to the core logic, and to EmbeddedICE for programming purposes. They are described in detail below.

Scan chains 0 and 1 allow access to the processor core for test and debug. They have the following length:

Scan chain 0

105 bits

Scan chain 1

33 bits

Each scan chain cell is fairly simple, and consists of a serial register and a multiplexer. The scan cells perform two basic functions:

capture

For input cells, the capture stage involves copying the value of the system input to the core into the serial register.

For output cells, capture involves placing the value of a core’s output into the serial register.

shift

For input cells, during shift, this value is output serially. The value applied to the core from an input cell is either the system input or the contents of the serial register, and this is controlled by the multiplexer.

For output cells, during shift, this value is serially output as before. The value applied to the system from an output cell is either the core output, or the contents of the serial register.

Figure 8.5. Input scan cell

All the control signals for the scan cells are generated internally by the TAP controller. The action of the TAP controller is determined by the current instruction, and the state of the TAP state machine. This is described in the following section.

Operating modes

The scan chains have three basic modes of operation. These are selected by the various TAP controller instructions.

SYSTEM mode

The scan cells are idle. System data is applied to inputs, and core outputs are applied to the system.

INTEST mode

The core is internally tested. The data serially scanned in is applied to the core, and the resulting outputs are captured in the output cells and scanned out.

EXTEST mode

Data is scanned onto the core's outputs and applied to the external system. System input data is captured in the input cells and then shifted out.

Note

The scan cells are not fully JTAG-compliant in that they do not have an Update stage. Therefore, while data is being moved around the scan chain, the contents of the scan cell is not isolated from the output. Thus the output from the scan cell to the core or to the external system could change on every scan clock.

This does not affect ARM7DMT because its internal state does not change until it is clocked. However, the rest of the system needs to be aware that every output could change asynchronously as data is moved around the scan chain. External logic must ensure that this does not harm the rest of the system.

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