8.7.6. Scan chain 0

Scan chain 0 is intended primarily for inter-device testing (EXTEST), and testing the core (INTEST). Scan chain 0 is selected via the SCAN_N instruction.

Serial testing the core

INTEST allows serial testing of the core. The TAP Controller must be placed in INTEST mode after scan chain 0 has been selected.

  • During CAPTURE-DR, the current outputs from the core’s logic are captured in the output cells.

  • During SHIFT-DR, this captured data is shifted out while a new serial test pattern is scanned in, thus applying known stimuli to the inputs.

  • During RUN-TEST/IDLE, the core is clocked. Normally, the TAP controller should only spend 1 cycle in RUN-TEST/IDLE.

The whole operation may then be repeated.

See ARM7DMT Core Clocks for details of the core’s clocks during test and debug.

Inter‑device testing

EXTEST allows inter-device testing, which is useful for verifying the connections between devices on a circuit board. The TAP Controller must be placed in EXTEST mode after scan chain 0 has been selected.

  • During CAPTURE-DR, the current inputs to the core's logic from the system are captured in the input cells.

  • During SHIFT-DR, this captured data is shifted out while a new serial test pattern is scanned in, thus applying known values on the core’s outputs.

  • During UPDATE-DR, the value shifted into the data bus D[31:0] scan cells appears on the outputs. For all other outputs, the value appears as the data is shifted round.

Note

During RUN-TEST/IDLE, the core is not clocked.

The operation may then be repeated. The ordering of signals on scan chain 0 is outlined in Table 8.3.

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