8.8.1. Clock switch during debug

When ARM7DMT is in the debug state, the core is clocked by DCLK under the control of the TAP state machine, and MCLK may free run. The selected clock is output on the signal ECLK for use by the external system.


When the CPU core is being debugged and is running from DCLK, nWAIT has no effect.

When ARM7DMT enters debug state, it must switch from MCLK to DCLK. This is handled automatically by logic in the ARM7DMT. On entry to debug state, ARM7DMT asserts DBGACK in the HIGH phase of MCLK. The switch between the two clocks occurs on the next falling edge of MCLK. This is shown in Figure 8.6.

Figure 8.6. Clock Switching on entry to debug state

ARM7DMT is forced to use DCLK as the primary clock until debugging is complete. On exit from debug, the core must be allowed to synchronize back to MCLK. This must be done in the following sequence:

  1. The final instruction of the debug sequence must be shifted into the data bus scan chain and clocked in by asserting DCLK.

  2. At this point, BYPASS must be clocked into the TAP instruction register.

  3. ARM7DMT now automatically resynchronizes back to MCLK and starts fetching instructions from memory at MCLK speed.

Please refer also to Exit from debug state.

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