8.9.2. Determining system state

In order to meet the dynamic timing requirements of the memory system, any attempt to access system state must occur synchronously with it. Thus, ARM7DMT must be forced to synchronize back to system speed. This is controlled by the 33rd bit of scan chain 1.

Any instruction may be placed in scan chain 1 with bit 33 (the BREAKPT bit) LOW. This instruction is then executed at debug speed. To execute an instruction at system speed, the instruction prior to it must be scanned into scan chain 1 with bit 33 set HIGH.

After the system speed instruction has been scanned into the data bus and clocked into the pipeline, the BYPASS instruction must be loaded into the TAP controller. This makes the ARM7DMT automatically synchronize back to MCLK (the system clock), executes the instruction at system speed, and then re-enters debug state and switches itself back to the internally generated DCLK. When the instruction has completed, DBGACK is HIGH and the core will have switched back to DCLK. At this point, INTEST can be selected in the TAP controller, and debugging can resume.

In order to determine that a system speed instruction has completed, the debugger must look at both DBGACK and nMREQ. In order to access memory, ARM7DMT drives nMREQ LOW after it has synchronized back to system speed. This transition is used by the memory controller to arbitrate whether ARM7DMT can have the bus in the next cycle. If the bus is not available, ARM7DMT may have its clock stalled indefinitely.

Therefore, the only way to tell that the memory access has completed, is to examine the state of both nMREQ and DBGACK. When both are HIGH, the access has completed. Usually, the debugger would be using EmbeddedICE to control debugging, and by reading EmbeddedICE’s status register, the state of nMREQ and DBGACK can be determined. Refer to Chapter 9 EmbeddedICE Macrocell for more details.

By the use of system speed load multiples and debug speed store multiples, the state of the system’s memory can be fed back to the debug host.


There are restrictions on which instructions may have the 33rd bit set. The only valid instructions where this bit can be set are:

  • loads

  • stores

  • load multiple

  • store multiple

See also Exit from debug state.

When ARM7DMT returns to debug state after a system speed access, bit 33 of scan chain 1 is set HIGH. This gives the debugger information about why the core entered debug state the first time this scan chain is read.

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