9.2.3. The control registers

Control Value and Control Mask registers are mapped identically in the lower 8 bits. Bit 8 of the control value register is the ENABLE bit, which cannot be masked.

Figure 9.3. Watchpoint control value and mask format

The bits have the following functions:


compares against the not‑read/write signal from the core in order to detect the direction of bus activity. nRW is 0 for a read cycle and 1 for a write cycle.


compares against the MAS[1:0] signal from the core in order to detect the size of bus activity. The encoding is shown in the following table.

Table 9.2. MAS[1:0] signal encoding

bit 1bit 0Data size

detects whether the current cycle is an instruction fetch (nOPC = 0) or a data access (nOPC = 1).


compares against the not‑translate signal from the core in order to distinguish between User mode (nTRANS = 0) and non-User mode (nTRANS = 1) accesses.


is an external input to EmbeddedICE which allows the watchpoint to be dependent upon an external condition. The EXTERN input for Watchpoint 0 is labelled EXTERN0 and the EXTERN input for Watchpoint 1 is labelled EXTERN1.


can be connected to the chain output of another watchpoint in order to implement, for example, debugger requests of the form “breakpoint on address YYY only when in process XXX”.

In the ARM7DMT-EmbeddedICE, the CHAINOUT output of Watchpoint 1 is connected to the CHAIN input of Watchpoint 0. The CHAINOUT output is derived from a latch; the address/control field comparator drives the write enable for the latch and the input to the latch is the value of the data field comparator. The CHAINOUT latch is cleared when the Control Value register is written or when nTRST is LOW.


can be connected to the range output of another watchpoint register. In the ARM7DMT EmbeddedICE, the RANGEOUT output of Watchpoint 1 is connected to the RANGE input of Watchpoint 0. This allows the two watchpoints to be coupled for detecting conditions that occur simultaneously, for example, in range-checking.


only exists in the value register and it cannot be masked. If a watchpoint match occurs, the BREAKPT signal is asserted only when the ENABLE bit is set.

For each of the bits [8:0] in the Control Value register, there is a corresponding bit in the Control Mask register. This removes the dependency on particular signals.

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E