9.8.1. Debug comms channel registers

The Debug Comms Control register is read‑only and allows synchronized handshaking between the processor and the debugger.

Figure 9.7. Debug comms control register

The function of each register bit is described below:

Bits [31:28]

contain a fixed pattern which denotes the EmbeddedICE version number, in this case 0001.

Bit [1]

denotes whether the Comms Data Write register is free (from the processor’s point of view).

From the processor’s point of view:

  • If the Comms Data Write register is free (W=0), new data may be written.

  • If it is not free (W=1), the processor must poll until W=0.

From the debugger’s point of view, if W=1, new data has been written which may then be scanned out.

Bit [0]

denotes whether there is some new data in the Comms Data Read register.

From the processor’s point of view:

  • If R=1, there is some new data which may be read via an MRC instruction.

From the debugger’s point of view:

  • If R=0, the Comms Data Read register is free and new data may be placed there through the scan chain.

  • If R=1, this denotes that data previously placed there through the scan chain has not been collected by the processor and so the debugger must wait.

From the debugger’s point of view, the registers are accessed via the scan chain in the usual way. From the processors point of view, these registers are accessed via coprocessor register transfer instructions.

Instructions

The following instructions should be used.

This instruction returns the Debug Comms Control register into Rd.

MRC CP14, 0, Rd, C0, C0

This instruction writes the value in Rn to the Comms Data Write register.

MCR CP14, 0, Rn, C1, C0

This instruction returns the Debug Data Read register into Rd.

MRC CP14, 0, Rd, C1, C0

Note

As the THUMB instruction set does not contain coprocessor instructions, it is recommended that these are accessed via SWI instructions when in THUMB state.

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