10.2.1. Using BWAIT

The BWAIT signal is used to insert entire BCLK cycles into the bus cycle timing. BWAIT may only change when BCLK is LOW, and extends the memory access by inserting BCLK cycles into the access whilst BWAIT is asserted.

Figure 11.4 shows the use of BWAIT in more detail.

Memory cycles

It is preferable to use BWAIT to extend memory cycles, rather than stretching BCLK externally to the device because it is possible for the core to be accessing the Cache while bus activity is occurring. This allows the maximum performance, as the Core can to continue execution in parallel with the memory bus activity. All BCLK cycles are available to the CPU and Cache, regardless of the state of BWAIT.

In some circumstances, it may be desirable to stretch BCLK phases in order to match memory timing which is not an integer multiple of BCLK. There are certain cases where this results in a higher performance than using BWAIT to extend the access by an integer number of cycles.

CPU and Cache operation

CPU and Cache operation can only continue in parallel with buffered writes to the external bus. For all read accesses, the CPU is stalled until the bus activity has completed. So, if read accesses can be achieved faster by stretching BCLK rather than using BWAIT, this results in improved performance. An example of where this may be useful would be to interface to a ROM which has a cycle time of 2.5 times the BCLK period.

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