10.3.2. Synchronous and asynchronous modes

When not using the fastbus extension, the ARM720T bus interface has two distinct modes of operation:

These are selected by tying SnA either HIGH or LOW.

FCLK and BCLK

The two modes differ in the relationship between FCLK and BCLK:

  • In asynchronous mode (SnA LOW), the clocks may be completely asynchronous and of unrelated frequency.

  • In synchronous mode (SnA HIGH), BCLK may only make transitions before the falling edge of FCLK.

In systems where a satisfactory relationship exists between FCLK and BCLK, synchronization penalties can be avoided by selecting the synchronous mode of operation.

Asynchronous mode

In this mode, FCLK and BCLK may be completely asynchronous. You should select this mode by tying SnA LOW when the two clocks are of unrelated frequency.

There is a synchronization penalty whenever the internal core clock switches between the two input clocks. This penalty is symmetrical, and varies between zero and a whole period of the clock to which the core is resynchronizing:

  • when changing from FCLK to BCLK, the average resynchronisation penalty is half an BCLK period

  • when changing from BCLK to FCLK, the average resynchronisation penalty is half an FCLK period.

Synchronous mode

You select this mode by tying SnA HIGH. In this mode, here is a tightly defined relationship between FCLK and BCLK, in that BCLK may only make transitions on the falling edge of FCLK. Some jitter between the two clocks is permitted, but BCLK must meet the setup and hold requirements relative to FCLK.

Figure 10.3. Relationship of FCLK and BCLK in synchronous mode

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