11.2.1. Single‑word memory access

A simple single‑word memory access is shown in Figure 11.1.

Figure 11.1. Simple single-cycle access

The access starts with the address being broadcast. This can be used for decoding, but the access is not committed until BTRAN[1:0] (Bus Transaction Type) signals a sequential cycle in the following HIGH phase of BCLK. This indicates that the next cycle is a memory access cycle.

In this example, BTRAN[1:0] returns to Address after a single cycle, indicating that there will be a single memory access cycle, followed by an address cycle. The data is transferred on the falling edge of BCLK at the end of the sequential cycle.

Therefore, a memory access consists of:

The initial address cycle allows the memory controller more time to decode the address. See Table 11.1 for the encoding of BTRAN[1:0].

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