11.2.2. Sequential accesses

ARM720T can perform sequential bursts of accesses. These consist of:

See Figure 11.2. After the initial address cycle, the address is pipelined by 1/2 a bus cycle from the data.

Note

BTRAN[1:0] is pipelined by a bus cycle from the data. If BWAIT is being used to stretch cycles, BTRAN[1:0] no longer refers to the next BCLK cycle, but rather to the next bus cycle. See BWAIT.

Figure 11.2. Simple sequential access

Sequential bursts can occur on word or halfword accesses, and are always in the same direction, that is, Read (BWRITE LOW) or Write (BWRITE HIGH).

A memory controller should always qualify the use of the address with BTRAN[1:0]. There are certain circumstances in which a new address can be broadcast on the address bus, but BTRAN[1:0] does not signal a sequential access. This only happens when an internal (Protection Unit generated) abort occurs.

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E
Non-Confidential