11.2.3. Bus accesses

The minimum interval between bus accesses can occur after a buffered write. In this case, there may only be a single address cycle between two memory cycles to non‑sequential addresses. This means that the address for the second access is broadcast on BA[31:0] during the HIGH phase of the final memory cycle of the buffered write.

See Figure 11.3 for more information.

Figure 11.3. Minimum interval between bus accesses

This is the closest case of back-to-back cycles on the bus, and the memory controller should be designed to handle this case. In high-speed systems one solution is to use BWAIT to increase the decode and access time available for the second access.

Note

Memory and peripheral strobes should not be direct decodes of the address bus. This could result in their changing during the last cycle of a write burst.

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