11.9.2. Halfword operations

A halfword store (STRH) repeats the bottom 16 bits of the source register twice across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystems to store the data.

Little-endian operation

A halfword load (LDRH) expects the data on data bus inputs 15 through 0 if the supplied address is on a word boundary, or on data bus inputs 31 through 16 if it is a word address plus two bytes. The selected halfword is placed in the bottom 16 bits of the destination register. The other two bytes on the databus are ignored. See Figure 11.5.

Big-endian operation

A halfword load (LDRH) expects the data on data bus inputs 31 through 16 if the supplied address is on a word boundary, or on data bus inputs 15 through 0 if it is a word address plus two bytes. The selected halfword is placed in the bottom 16 bits of the destination register. The other 2 bytes on the databus are ignored. See Figure 11.6.

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