11.10.1. Arbitration

Efficient arbitration is important to reduce “dead-time” between successive masters being active on the bus. The bus protocol supports pipelined arbitration, such that arbitration for the next transfer is performed during the current transfer.

The arbitration protocol is defined, but the prioritization is flexible and left to the application. Typically, the Test Interface would be given the highest priority to ensure test access under all conditions. Every system must also include a default bus master, which is granted the bus when no bus masters are requesting it.

The request signal, AREQ, from each bus master to the arbiter indicates that the bus master requires the bus. The grant signal from the arbiter to the bus master, AGNT, indicates that the bus master is currently the highest priority master requesting the bus.

The bus master:

The shared bus lock signal, BLOK, indicates to the arbiter that the following transfer is indivisible from the current transfer and no other bus master should be given access to the bus.

A bus master must always drive a valid level on the BLOK signal when granted the bus to ensure the arbitration process can continue, even if the bus master is not performing any transfers.

The arbiter functions as follows:

  1. Bus masters assert AREQ during the HIGH phase of BCLK.

  2. The arbiter samples all AREQ signals on the falling edge of BCLK.

  3. During the LOW phase of BCLK, the arbiter also samples the BLOK signal and then asserts the appropriate AGNT signal.

    If BLOK is LOW, the arbiter grants the highest priority bus master.

    If BLOK is HIGH, the arbiter keeps the same bus master granted.

The arbiter can update the grant signals every bus cycle; however, a new bus master can only become granted and start driving the bus when the current transfer completes, as indicated by BWAIT being LOW. Therefore, it is possible for the potential next bus master to change during waited transfers.

The BLOK signal is ignored by the arbiter during the single cycle of handover between two different bus masters.

If no bus masters are requesting the bus, the arbiter must grant the default bus master. The arbitration protocol is defined, but the prioritization is flexible and left to the application. A simple fixed-priority scheme may be used; alternatively, a more complex scheme can be implemented if required by the application.

Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E
Non-Confidential