12.7.1. Status packet bit positions

Table 12.3. Status packet bit positions bits [31:0]

BitARM7TDMI TestARM720T TestNotes
31

BUSDIS

Bus Disable

  
30SCREG[3]Scan chain register

SCREG[3]

Scan chain register

 
29

SCREG[2]

Scan chain register

SCREG[2]

Scan chain register

 
28

SCREG[1]

Scan chain register

SCREG[1]

Scan chain register

 
27

SCREG[0]

Scan chain register

SCREG[0]

Scan chain register

 
26

HIGHZ

HIGHZ instruction in TAP controller

HIGHZ

HIGHZ instruction in TAP controller

 
25

nTDOEN

not TDO enable

nTDOEN

not TDO enable

 
24

DBGRQI

Internal debug request

DBGRQI

Internal debug request

 
23

RANGEOUT0

ICEbreaker Rangeout0

RANGEOUT0

ICEbreaker Rangeout0

 
22

RANGEOUT1

ICEbreaker Rangeout1

RANGEOUT1

ICEbreaker Rangeout1

 
21

COMMRX

Communications channel receive

COMMRX

Communications channel receive

 
20

COMMTX

Communications channel transmit

COMMTX

Communications channel transmit

 
19

DBGACK

Debug acknowledge

DBGACK

Debug acknowledge

 
18

TDO

Test data out

TDO

Test data out

 
17

nENOUT

Not enable output.

nENOUT

Not enable output

nENOUT is only valid during the data access cycle, so MCLKENABLE is used to clock a transparent latch that will capture the correct state.
16

nENOUTI

Not enable output

PROTWATCH[3]

Protection Unit test output

nENOUTI as nENOUT
15

TBIT

Thumb state

PROTWATCH[2]

Protection Unit test output

 
14

nCPI

Not Coprocessor instruction

  
13

nM[4]

Not processor mode

CAMWATCH[2]

Replacement test output

 
12

nM[3]

Not processor mode

CAMWATCH[1]

Replacement test output

 
11

nM[2]

Not processor mode

CAMWATCH[0]

Replacement test output

 
10

nM[1]

Not processor mode

IDCWATCH[3]

Cache test output

 
9

nM[0]

Not processor mode

IDCWATCH[2]

Cache test output

 
8

nTRANS

Not memory translate

IDCWATCH[1]

Cache test output

 
7

nEXEC

Not executed

IDCWATCH[0]

Cache test output

 
6

LOCK

Locked operation.

LOCK

Locked operation

 
5

MAS[1]

Memory Access Size

MAS[1]

Memory Access Size

 
4

MAS[0]

Memory Access Size

MAS[0]

Memory Access Size

 
3

nOPC

Not op-code fetch

nENOUT

Not enable output

 
2

nRW

Not read/write

nRW

Not read/write

 
1

nMREQ

Not memory request

nMREQ

Not memory request

 
0

SEQ

Sequential address

SEQ

Sequential address

 
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