12.7.2. Control packet bit positions

Table 12.4. Control Packet bit positions bits [31:0]

BitARM7TDMI InputARM720T InputNotes
31

TESTCPU

ARM7TDMI test enable

TESTCPU

ARM7TDMI test enable

 
30 

TAGTEST

TAG test mode enable

 
29 

RAMTEST

RAM test mode enable

 
28

nENIN

NOT enable input.

FORCEFCLK

Clock select override

nENIN is gated with MCLKENABLE, so it is only valid (LOW) during data access.
27

SDOUTBS

Boundary scan serial output data

MMUTEST

MMU test mode enable

 
26

TBE

Test bus enable

  
25

APE

Address pipeline enable

  
24

BL[3]

Byte Latch Control

 ANDed with MCLKENABLE, so is only valid during data access cycle.
23

BL[2]

Byte Latch Control

 ANDed with MCLKENABLE, so is only valid during data access cycle.
22

BL[1]

Byte Latch Control

 ANDed with MCLKENABLE, so is only valid during data access cycle.
21

BL[0]

Byte Latch Control

 ANDed with MCLKENABLE, so is only valid during data access cycle.
20

TMS

Test Mode Select

TMS

Test Mode Select

 
19

TDI

Test Data in

TDI

Test Data in

 
18

TCK

Test clock

TCK

Test clock

ANDed with MCLKENABLE and BCLK.
17

nTRST

Not Test Reset.

nTRST

Not Test Reset

 
16

EXTERN1

External input 1

EXTERN1

External input 1

 
15

EXTERN0

External input 0

EXTERN0

External input 0

 
14

DBGRQ

Debug request

DBGRQ

Debug request

 
13

BREAKPT

Breakpoint

BREAKPT

Breakpoint

 
12

DBGEN

Debug Enable

DBGEN

Debug Enable

 
11

ISYNC

Synchronous interrupts

  
10

BIGEND

Big Endian configuration

WINCE EN

WinCe Enhancements enable

 
9

CPA

Coprocessor absent

CPA

Coprocessor absent

 
8

CPB

Coprocessor busy

CPB

Coprocessor busy

 
7

ABE

Address bus enable

SnA

Clock Configuration

This should normally be set HIGH, as if the bus is tri-stated (ABE low), then it is not possible to read address values.
6

ALE

Address latch enable

ALE

Address latch enable

 
5

DBE

Data Bus Enable

FASTBUS

Clock configuration

DBE to the ARM7DMT is ANDed with the state machine generated DBE and BCLK to prevent bus conflict.
4

nFIQ

Not fast interrupt request.

nFIQ

Not fast interrupt request

 
3

nIRQ

Not interrupt request

nIRQ

Not interrupt request

 
2

ABORT

Memory Abort

ABORT

Memory Abort

 
1

nWAIT

Not wait

nWAIT

Not wait

ANDed with MCLKENABLE, so that the core state can only change during the data access cycle.
0

nRESET

Not reset

nRESET

Not reset

 
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