ARM® 720T Datasheet

Revision: r0p0


Table of Contents

1. Introduction
1.1. Overview
1.2. Block Diagram
1.3. Coprocessors
1.4. Instruction Set Overview
1.4.1. ARM instruction set
1.4.2. THUMB Instruction Set
2. Signal Desriptions
2.1. AMBA Interface Signals
2.2. Coprocessor Interface Signals
2.3. JTAG Signals
2.4. Debugger Signals
2.5. Miscellaneous Signals
3. Programmers Model
3.1. Processor Operating States
3.1.1. Switching state
3.2. Memory Formats
3.2.1. Big‑endian format
3.2.2. Little‑endian format
3.3. Instruction Length, Data Types, and Operating Modes
3.3.1. Instruction length
3.3.2. Data types
3.3.3. Operating modes
3.4. Registers
3.4.1. The ARM state register set
3.4.2. The THUMB state register set
3.4.3. The relationship between ARM and THUMB state registers
3.4.4. Accessing Hi registers in THUMB state
3.5. The Program Status Registers
3.5.1. The condition code flags
3.5.2. The control bits
3.6. Exceptions
3.6.1. Action on entering an exception
3.6.2. Action on leaving an exception
3.6.3. Exception entry/exit summary
3.6.4. FIQ
3.6.5. IRQ
3.6.6. Abort
3.6.7. Software interrupt
3.6.8. Undefined instruction
3.6.9. Exception vectors
3.6.10. Exception priorities
3.7. Reset
3.8. Relocation of Low Virtual Addresses by Process Identifier
3.9. Implementation-defined Behaviour of Instructions
4. Configuration
4.1. Overview
4.1.1. Compatibility
4.1.2. Notation
4.2. Internal Coprocessor Instructions
4.3. Registers
4.3.1. Register 0: ID register
4.3.2. Register 1: Control register
4.3.3. Register 2: Translation table base register
4.3.4. Register 3: Domain access control register
4.3.5. Register 4: Reserved
4.3.6. Register 5: Fault Status Register
4.3.7. Register 6: Fault Address Register
4.3.8. Register 7: Cache Operations
4.3.9. Register 8: TLB Operations
4.3.10. Registers 9 – 12: Reserved
4.3.11. Register 13: Process Identifier
4.3.12. Registers 14-15: Reserved
5. Instruction and Data Cache (IDC)
5.1. Overview of the Instruction and Data Cache
5.1.1. IDC operation
5.1.2. Cacheable bit
5.1.3. DC operation
5.1.4. Read-lock-write
5.2. IDC Validity
5.2.1. Software IDC flush
5.2.2. Doubly‑mapped space
5.3. IDC Enable/Disable and Reset
6. Write Buffer
6.1. Overview
6.1.1. Bufferable bit
6.2. Write Buffer Operation
6.2.1. Bufferable write
6.2.2. Unbufferable writes
6.2.3. Read-lock-write
7. Memory Management Unit (MMU)
7.1. Overview
7.1.1. Memory accesses
7.1.2. Domains
7.1.3. TLB
7.1.4. Effect of reset
7.2. MMU Program Accessible Registers
7.3. Address Translation Process
7.3.1. Translation table base
7.3.2. Level 1 fetch
7.4. Level 1 Descriptor
7.5. Page Table Descriptor
7.6. Section Descriptor
7.7. Translating Section References
7.8. Level 2 Descriptor
7.9. Translating Small Page References
7.10. Translating Large Page References
7.11. MMU Faults and CPU Aborts
7.12. Fault Address and Fault Status Registers (FAR & FSR)
7.13. Domain Access Control
7.14. Fault Checking Sequence
7.14.1. Alignment fault
7.14.2. Translation fault
7.14.3. Domain fault
7.14.4. Permission fault
7.15. External Aborts
7.16. Interaction of the MMU, IDC and Write Buffer
7.16.1. Enabling the MMU
7.16.2. Disabling the MMU
8. Debug Interface
8.1. Overview
8.1.1. Debug extensions
8.1.2. Pullup resistors
8.1.3. Instruction register
8.2. Debug Systems
8.3. Entering Debug State
8.3.1. Entering debug state on breakpoint
8.3.2. Entering debug state on watchpoint
8.3.3. Entering debug state on debug-request
8.4. Scan Chains and JTAG Interface
8.4.1. Scan limitations
8.4.2. The JTAG state machine
8.5. Reset
8.6. Public Instructions
8.7. Test Data Registers
8.7.1. Bypass register
8.7.2. ARM7DMT device identification (ID) code register
8.7.3. Instruction register
8.7.4. Scan chain select register
8.7.5. Overview of scan chains 0,1, 2 and 15
8.7.6. Scan chain 0
8.7.7. Scan chain 1
8.7.8. Scan chain 2
8.7.9. Scan chain 3
8.7.10. Scan chain 15
8.8. ARM7DMT Core Clocks
8.8.1. Clock switch during debug
8.9. Determining the Core and System State
8.9.1. Determining the core’s state
8.9.2. Determining system state
8.9.3. Determining system control coprocessor state
8.9.4. Exit from debug state
8.10. The PC During Debug
8.10.1. Breakpoint
8.10.2. Watchpoint
8.10.3. Watchpoint with another exception
8.10.4. Debug request
8.10.5. System‑speed access
8.10.6. Summary of return address calculations
8.11. Priorities and Exceptions
8.11.1. Breakpoint with prefetch abort
8.11.2. Interrupt
8.11.3. Data aborts
8.12. Scan Interface Timing
9. EmbeddedICE Macrocell
9.1. Overview
9.1.1. Disabling EmbeddedICE
9.1.2. EmbeddedICE timing
9.2. The Watchpoint Registers
9.2.1. Programming and reading watchpoint registers
9.2.2. Using the mask registers
9.2.3. The control registers
9.3. Programming Breakpoints
9.3.1. Hardware breakpoints
9.3.2. Software breakpoints
9.4. Programming Watchpoints
9.4.1. Programming restriction
9.5. The Debug Control Register
9.6. Debug Status Register
9.7. Coupling Breakpoints and Watchpoints
9.7.1. Example
9.8. Debug Communications Channel
9.8.1. Debug comms channel registers
9.8.2. Communications via the comms channel
9.8.3. Message transfer
10. Bus Clocking
10.1. Introduction
10.1.1. Standard mode
10.1.2. Fastbus extension
10.2. Fastbus Extension
10.2.1. Using BWAIT
10.3. Standard Mode
10.3.1. Memory access
10.3.2. Synchronous and asynchronous modes
11. AMBA Interface
11.1. ASB Bus Interface Signals
11.2. Cycle Types
11.2.1. Single‑word memory access
11.2.2. Sequential accesses
11.2.3. Bus accesses
11.3. Addressing Signals
11.4. Memory Request Signals
11.5. Data Signal Timing
11.6. Slave Response Signals
11.6.1. BERROR
11.6.2. BWAIT
11.6.3. Other slave responses
11.7. Maximum Sequential Length
11.8. Read-Lock-Write
11.9. Big-Endian / Little-Endian Operation
11.9.1. Word operations
11.9.2. Halfword operations
11.9.3. Byte operations
11.10. Multi-master Operation
11.10.1. Arbitration
11.11. Bus Master Handover
11.12. Default Bus Master
12. AMBA Test
12.1. Slave Operation (Test mode)
12.2. ARM720T Test Mode
12.3. ARM7DMT Core Test Mode
12.4. RAM Test Mode
12.5. TAG Test Mode
12.6. MMU Test Mode
12.7. Test Register Mapping
12.7.1. Status packet bit positions
12.7.2. Control packet bit positions

List of Figures

1.1. ARM720T block diagram
1.2. ARM instruction set formats
1.3. THUMB instruction set formats
3.1. Big-endian address of bytes within words
3.2. Little-endian addresses of bytes with words
3.3. Register organization in ARM state
3.4. Register organization in THUMB state
3.5. Mapping of THUMB state registers onto ARM state registers
3.6. Program status register format
4.1. MRC, MCR bit pattern
4.2. ID register read
4.3. ID register write
4.4. Register 1 read
4.5. Register 1 write
4.6. Register 2
4.7. Register 3
4.8. Register 4
4.9. Register 5
4.10. Register 6
4.11. Register 13
7.1. Translation table base register
7.2. Accessing the translation table first level descriptors
7.3. Level 1 Descriptors
7.4. Section translation
7.5. Page table entry (Level 2 Descriptor)
7.6. Small page translation
7.7. Large page translation
7.8. Domain access control register format
7.9. Sequence for checking faults
8.1. Typical debug system
8.2. ARM7DMT scan chain arrangement
8.3. Test access port (TAP) controller state transitions
8.4. ID register description
8.5. Input scan cell
8.6. Clock Switching on entry to debug state
8.7. Scan general timing
9.1. ARM7TDMI block diagram
9.2. EmbeddedICE block diagram
9.3. Watchpoint control value and mask format
9.4. Debug control register format
9.5. Debug status register format
9.6. Structure of TBIT, NMREQ, DBGACK, DBGRQ and INTDIS bits
9.7. Debug comms control register
10.1. Conceptual device clocking using the fastbus extension
10.2. Conceptual device clocking in standard mode
10.3. Relationship of FCLK and BCLK in synchronous mode
11.1. Simple single-cycle access
11.2. Simple sequential access
11.3. Minimum interval between bus accesses
11.4. Use of the BWAIT pin to stop ARM720T for 1 BCLK cycle
11.5. Little‑endian addresses of bytes within word
11.6. Big-endian addresses of bytes within word
11.7. Bus Master Handover
12.1. Running a test vector on the processor core
12.2. State machine for ARM720T and ARM7TDMI test
12.3. State machine for RAM test mode
12.4. State machine for TAG test mode
12.5. State machine for MMU test mode

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision BSeptempber 1997First draft of first release for r0p0
Revision C December 1997Update for next release
Revision D February 1998Change to Open Access
Revision E July 1998Logo, address changes, minor text changes
Copyright © 1997, 1998 ARM Limited. All rights reserved.DDI 0087E
Non-Confidential