ARM®940T Technical Reference manual 4.1. Introduction

4.1. Introduction

To reduce the effective memory access time, the ARM940T employs an Instruction Cache (I Cache), a Data Cache (D Cache) and a Write Buffer. The following sections describe the features and behavior of each of these blocks. The information in this chapter is organized as follows:

Cache architecture
Instruction cache
Data cache
The write buffer
Cache lock down.

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