The source GCLK applied
to the internal ARM9TDMI bus is dependent on the current selected
clock mode and the operation being performed. Refer to Clock Modes
for further details.
The ARM9TDMI core has two clocks, the memory clock GCLK, and an internally TCK generated clock, DCLK. During normal operation, the
core is clocked by GCLK, and
internal logic holds DCLK LOW.
When the ARM940T is in the debug state, the core is clocked by DCLK under control of the TAP state
machine, and GCLK may free run.
The selected clock is output on the ECLK signal
for use by the external system.
Note
When the core is being debugged and is running from DCLK, nWAIT has
no effect.
There are two cases in which the clocks switch—during debugging
and during testing.
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