The ARM940T has a 4KB Instruction Cache (I Cache) comprising 16 bytes (four words) arranged as four 64-way associative segments.

The I Cache uses the physical address generated by the processor core. It employs a policy of ‘allocate on read-miss’ and is always reloaded one cache line (four words) at a time, through the external interface.

The I Cache operation may be enabled or disabled by the CP15 control register, and is always disabled on reset. When enabled, the I Cache operation is further controlled by the (GCi) Gated Cacheable data bit stored in the protection unit, which selectively enables/disables caching for different memory regions. The GCi bits have the protection unit enable factored into them such that GCi = 1 only when a cacheable region is accessed AND the protection unit is enabled.

The I Cache and protection unit can be enabled with a single write to the CP15 control register, although at least one protection region should be programmed before the protection unit is enabled. Critical or frequently accessed instructions can be locked down into the I Cache with a granularity of 64 bytes.