The ARM940T has a 4KB Data Cache (D Cache) comprising 256 lines of 16 bytes (bytes words), arranged as four 64-way associative segments. The D Cache uses the physical address generated by the processor core. It employs an allocate on read-miss policy, and is always reloaded a cache line (four words) at a time through the external interface.

The D Cache supports both Write-back (WB) and Write-Through (WT) modes. For data stores that hit in the D Cache, in WB mode the cache line is updated, and an additional dirty bit associated with the cache line is set. This indicates that the internal version of the data differs from that in the external memory. In WT mode, a store that hits in the D Cache causes the cache line to be updated but not marked as dirty, as the data store is also written to the write buffer to keep the external memory consistent. In both WB and WT modes, a store that misses in the cache is sent to the write buffer. When a line fetch causes a cache line to be evicted from the D Cache, the dirty bit for the victim line is read and if the line contains valid and dirty data, it is written back to the write buffer before the line fill replaces it.

The Gated Cacheable Data (GCd) bit and the Gated Write Buffer Control (GBd) bit control the D Cache behavior. For this reason the protection unit must be enabled when the D Cache is enabled.