To provide a predictable code behavior in embedded systems, a mechanism for locking code and data into the Instruction and Data caches respectively is provided. This feature may be used, for example, to hold high-priority interrupt routines where there is a hard real-time constraint, or to hold the co-efficients of a DSP filter routine in order to reduce external bus traffic.

Locking down a region of the I Cache or D Cache is achieved by executing a short software routine, taking note of these requirements:

Lock down in the D Cache is achieved through use of CP15 register 9. I Cache lock down uses both CP15 registers 7 and 9.

As described in Cache architecture, the ARM940T I and D Caches comprise four segments, each with 64 lines of four words each. Each segment is 1KB in size. Lock down can be performed with a granularity of one line across each of the four segments; the smallest space which may be locked down is 16 words. Lock down starts at line zero, and can continue until 63 of the 64 lines are locked.