The cycle timing for this operation is shown in Figure 7.2.
In this example, four words of data are transferred. The number of words transferred is determined by how the coprocessor drives the CHSDE[1:0] and CHSEX[1:0] buses.
As with all other instructions, the ARM940T processor core performs the main instruction decode off the rising edge of the clock during the decode stage. From this, the core commits to executing the instruction, and so performs an instruction fetch. The coprocessor’s instruction pipeline should keep in step with the ARM940T by monitoring CPMREQ, a latched copy of the ARM9TDMI instruction memory request signal nIMREQ. Whenever nCPMREQ is LOW, an instruction fetch is occurring and CPID will be updated with fetched instruction in the next cycle. This means that the instruction currently on CPID should enter the decode stage of the coprocessor pipeline, and that the instruction in the decode stage of the coprocessor’s pipeline should enter its execute stage.
During the execute stage, the condition codes are combined with the flags to determine whether the instruction should be executed or not. The output CPPASS is asserted (HIGH) if the instruction in the execute stage of the coprocessor pipeline is:
a coprocessor instruction
has passed its condition codes.
If a coprocessor instruction busy-waits, CPPASS is asserted on every cycle until the coprocessor instruction is executed. If an interrupt occurs during busy-waiting, CPPASS is driven LOW, and the coprocessor should stop execution of the coprocessor instruction.
A further output, CPLATECANCEL, is used to cancel a coprocessor instruction when the instruction preceding it caused a data abort. This is valid on the rising edge of CPCLK on the cycle after the first execute cycle of the coprocessor instructions. CPLATECANCEL will only be asserted during the first memory cycle of a coprocessor instruction’s execution.
On the falling edge of the clock, the ARM940T processor core examines the coprocessor handshake signals CHSDE[1:0] or CHSEX[1:0]:
If a new instruction is entering the execute stage in the next cycle, it examines CHSDE[1:0]
If the coprocessor instruction currently in execute requires another execute cycle, it examines CHSEX[1:0].
The handshake signals encode one of four states:
- ABSENT
If there is no coprocessor attached which can execute the coprocessor instruction, the handshake signals indicate the ABSENT state. In this case, the ARM9TDMI processor core takes the undefined instruction exception.
- WAIT
If there is a coprocessor attached that can execute the instruction but not immediately, the coprocessor handshake signals should be driven to indicate that the ARM9TDMI processor core should stall until the coprocessor can catch up. This is known as the ‘busy-wait’ condition.
In this case, the ARM9TDMI processor core loops in an idle state, waiting for CHSEX[1:0] to be driven to another state, or for an interrupt to occur. If CHSEX[1:0] changes to ABSENT, the undefined instruction exception will be taken. If CHSEX[1:0] changes to GO or LAST, the instruction will proceed as described below.
If an interrupt occurs, the ARM9TDMI processor core is forced out of the busy-wait state. This is indicated to the coprocessor by the CPPASS signal going LOW. The instruction will be restarted at a later date and so the coprocessor must not commit to the instruction (change any of the coprocessor states) until it has seen CPPASS HIGH and when the handshake signals indicate the GO or LAST condition.
- GO
The GO state indicates that the coprocessor can execute the instruction immediately, and that it requires another cycle of execution. Both the ARM9TDMI processor core and the coprocessor must also consider the state of the CPPASS signal before actually committing to the instruction. For an LDC or STC instruction, the coprocessor instruction should drive the handshake signals with GO when two or more words still need to be transferred. When only one further word is required, the coprocessor should drive the handshake signals with the LAST condition.
In phase 2 of the execute stage, the ARM9TDMI processor core outputs the address for the LDC/STC. Also in this phase, DnMREQ is driven LOW, indicating to the memory system that a memory access is required at the data end of the device. The timing for the data on CPDOUT[31:0] for an LDC and CPDIN[31:0] for an STC is as shown in Figure 7.2.
- LAST
An LDC or STC can be used for more than one item of data. If this is the case, possibly after busy waiting, the coprocessor should drive the coprocessor handshake signals with a number of GO states, and in the penultimate cycle LAST. The LAST indicating that the next transfer is the final one. If there was only one transfer, the sequence would be [WAIT,[WAIT,...]],LAST.
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