If the data for an MCR operation is not available inside the ARM9TDMI pipeline during its first decode cycle, the ARM940T pipeline interlock for one or more cycles until the data is available. An example of this is where the register being transferred is the destination from a preceding LDR instruction. In this situation the MCR instruction will enter the decode stage of the coprocessor pipeline, and remain there for a number of cycles before entering the execute stage. Figure 7.4 gives an example of an interlocked MCR.

Figure 7.4. ARM940T interlocked MCR