ARM®940T Technical Reference manual 2.2.6. Register 5: Instruction and data space protection registers

2.2.6. Register 5: Instruction and data space protection registers

These registers contain the access permission bits for the instruction and data protection regions. The opcode_2 field of a MRC/MCR determines whether the instruction or data access permissions are to be programmed:

MCR/MRC p15,0,Rd,c5,co,0 Write/Read data space access permissions

MCR/MRC p15,0,Rd,c5,co,1 Write/Read instruction space access permissions

Each register contains the access permission bits, apn[1:0], for the eight areas of instruction or data memory.

All defined bits in the protection registers are set to zero at reset.

Table 2.7. Protection space register format

Register bit	Function
15:14	ap7[1:0] bits of area 7
13:12	ap6[1:0] bits of area 6
11:10	ap5[1:0] bits of area 5
9:8	ap4[1:0] bits of area 4
7:6	ap3[1:0] bits of area 3
5:4	ap2[1:0] bits of area 2
3:2	ap1[1:0] bits of area 1
1:0	ap0[1:0] bits of area 0

The values of the Iapn[1:0] and Dapn[1:0] bits define the access permission for each area of memory. The encoding is shown in Table 2.8.

All defined bits in the protection registers are set to zero at reset.

Table 2.8. Permission encoding

I/Dapn[1:0]	Permission
00	No access
01	Privileged mode access only
10	Privileged mode full access, user mode read only
11	Full access

The use of register 5 discussed in Chapter 3 Protection Unit.

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