2.2.9. Register 9: Programming lockdown registers
These registers allow regions of the cache to be locked down.
The format is:
Table 2.16. Programming the lockdown registers
| ARM instructions | Lockdown register |
|---|
| MCR/MRC p15, 0, Rd, c9, c0, 0 | Data lockdown control |
| MCR/MRC p15, 0, Rd, c9, c0, 1 | Instruction lockdown control |
The format of the registers, Rd, transferred during this operation,
is shown below:
All defined bits in the lockdown registers are set to zero
at reset.
Table 2.17. Lockdown register format
| Register bit | Function |
|---|
| 31 | Load bit |
| 30:6 | Reserved |
| 5:0 | Cache index |
Note
The segment number is not specified because cache lines are
locked down across all four segments (16-word granularity). The
use of register 9 is discussed in Chapter 4 Caches and Write Buffer.
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