| Copyright © 1998 ARM Limited. All rights reserved. | DDI0092B |
| Non-Confidential | |
 PDF version | |
| Home > Caches and Write Buffer > Instruction cache > Instruction cache operation |
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When the I Cache is enabled, it is searched when the processor requests an instruction:
Data is returned to the core regardless of the state of the GCi bit.
The GCi bit is examined:
If this bit is 1, a cacheable code area and protection unit enabled — a linefetch of four words is performed. The data is written into a randomly chosen line in the I Cache.
If this bit is 0, a single-word external access is performed to fetch the requested instruction. The cache is not updated.
Locked down code is always found on I Cache searches. Lines containing locked down code cannot be selected for replacement during a linefetch.
| Copyright © 1998 ARM Limited. All rights reserved. | DDI0092B |
| Non-Confidential | |
| PDF version | |
| Home > Caches and Write Buffer > Instruction cache > Instruction cache operation |