ARM ® 940T TechnicalReference manual

Revision: 0


Table of Contents

Preface
About this document
Intended audience
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Overview
1.1. The ARM940T
2. Programmer’s Mode
2.1. Introduction
2.2. ARM940T CP15 registers
2.2.1. CP15 register map summary
2.2.2. Register 0
2.2.3. Register 1: Control register
2.2.4. Register 2: Cacheable registers
2.2.5. Register 3: Write buffer control register
2.2.6. Register 5: Instruction and data space protectionregisters
2.2.7. Register 6: Protection region base / size registers
2.2.8. Register 7
2.2.9. Register 9: Programming lockdown registers
2.2.10. Register 15: Test register
2.2.11. Reserved registers
3. Protection Unit
3.1. Introduction
3.2. Enabling the protection unit
3.3. Memory regions
3.3.1. Area size
3.3.2. Base address
3.3.3. Region attributes
3.4. Overlapping regions
3.4.1. Background regions
4. Caches and Write Buffer
4.1. Introduction
4.2. Cache architecture
4.3. Instruction cache
4.3.1. Instruction cache operation
4.3.2. Instruction cache validity
4.3.3. Flushing the entire cache
4.3.4. Flushing a single cache line
4.3.5. Instruction cache enable/disable and reset
4.4. Data cache
4.4.1. Gated cacheable data bit
4.4.2. Gated write buffer control bit
4.4.3. Data cache operation
4.4.4. Data cache validity
4.4.5. Data cache clean and/or flush
4.4.6. Data cache enable/disable and reset
4.5. The write buffer
4.5.1. Write buffer operation
4.5.2. Enabling/disabling the write buffer
4.6. Cache lock down
4.6.1. Locking down the caches
5. Clock Modes
5.1. Overview
5.2. FastBus mode
5.3. Sychronous mode
5.4. Asynchronous mode
6. Bus Interface Unit
6.1. Introduction
6.2. ASB transfers
6.3. Burst accesses
6.4. Buffered writes
6.5. LDM operations from a non-cached region
6.6. STM operation to a non-cached region
6.7. External aborts
6.8. SWP instruction
6.9. Memory access order
7. ARM940T Coprocessor Interface
7.1. Overview
7.1.1. Internal coprocessors
7.1.2. External coprocessors
7.2. LDC/STC
7.2.1. Coprocessor Handshake Encoding
7.3. MCR/MRC
7.4. Interlocked MCR
7.5. CDP
7.6. Privileged instructions
7.7. Busy-waiting and interrupts
8. Debug Support
8.1. Overview
8.2. Debug systems
8.3. Debug interface signals
8.3.1. Entry into debug state on breakpoint
8.3.2. Breakpoints and exceptions
8.3.3. Watchpoints
8.3.4. Watchpoints and exceptions
8.3.5. Debug request
8.3.6. Actions of the ARM940T in debug state
8.4. Scan chains and JTAG interface
8.5. The JTAG state machine
8.5.1. Reset
8.5.2. Pullup resistors
8.5.3. Instruction register
8.5.4. Public instructions
8.6. Test data registers
8.6.1. Bypass register
8.6.2. ARM940T device identification (ID) code register
8.6.3. Instruction register
8.6.4. Scan chain select register
8.6.5. Scan chains 0, 1, 2, 3, 4, 5, and 15
8.7. ARM940T core clocks
8.8. Clock switching during debug
8.9. Clock switching during test
8.10. Determining the core and system state
8.10.1. Determining the core state
8.10.2. Determining system state
8.10.3. Instructions which may have the SYSSPEED bit set
8.11. Exit from debug state
8.12. The PC’s behavior during debug
8.12.1. Breakpoint
8.12.2. Watchpoint
8.12.3. Watchpoint with another exception
8.12.4. Watchpoint and breakpoint
8.12.5. Debug request
8.12.6. System speed accesses
8.12.7. Summary of return address calculations
8.13. EmbeddedICE
8.13.1. Register map
8.13.2. Control registers
8.13.3. Debug control register
8.13.4. Debug status register
8.13.5. Vector catch register
8.14. Vector catching
8.15. Single stepping
8.16. Debug communications channel
8.16.1. Debug comms channel registers
8.16.2. Communications via the comms channel
8.16.3. Software polling communication
8.16.4. Interrupt driven communications
8.17. The debugger’s view of the cache
9. TrackingICE
9.1. Overview
9.2. Timing requirements
9.3. TrackingICE outputs
10. Test Issues
10.1. Introduction
10.2. Scan chain 0 bit order
11. Instruction Cycle Summary and Interlocks
11.1. Introduction
11.2. Instruction cycle times
11.2.1. Key to tables
11.2.2. Multiplier cycle counts
11.3. Interlocks
11.3.1. Example 1
11.3.2. Example 2
11.3.3. Example 3
11.3.4. Example 4
12. ARM940T AC Characteristics
12.1. Introduction
12.2. ARM940T timing diagrams
12.3. ARM940T timing parameters
A. ARM940T Signal Descriptions
A.1. AMBA signals
A.1.1. AMBA Bus Specification
A.2. Coprocessor interface signals
A.3. JTAG and TAP controller signals
A.4. Debug signals
A.5. Miscellaneous signals

List of Figures

1. Key to timing diagram conventions
1.1. ARM940T block diagram
3.1. ARM940T protection unit
3.2. Overlapping memory regions
4.1. ARM940T Instruction/Data cache addressmapping
4.2. 4KB cache used for ARM940T instructionand data caches
5.1. Sychronous clocking mode
5.2. Switching from FCLK to BCLK in sychronousmode
5.3. Asynchronous clocking mode
5.4. Switching from FCLK to BCLK in asynchronousmode
6.1. Sequential LDR accesses
6.2. Cache line fill
6.3. Write buffer allocation
6.4. LDM operation
6.5. STM operation
6.6. Simultaneous cache misses
7.1. ARM940T coprocessor clocking
7.2. ARM940T LDC / STC cycle timing
7.3. ARM940T MCR / MRC transfer timing
7.4. ARM940T interlocked MCR
7.5. ARM940T late cancelled CDP
7.6. ARM940T privileged instructions
7.7. ARM940T busy waiting and interrupts
8.1. Typical debug system
8.2. Breakpoint timing
8.3. Watchpoint entry with data processinginstruction
8.4. Watchpoint entry with branch
8.5. Test access port (TAP) controllerstate transitions
8.6. Clock switching on entry to debug state
8.7. Debug exit sequence
8.8. Debug state entry
8.9. ARM940T EmbeddedICE overview
8.10. Debug comms control register
9.1. Using TrackingICE
11.1. Single load interlock timing
11.2. Two cycle load interlock
11.3. LDM interlock
11.4. LDM dependent interlock
12.1. ARM940T FCLK timed coprocessor interface
12.2. ARM940T BCLK timed coprocessor interface
12.3. ARM940T FCLK related signal timing
12.4. ARM940T BCLK related signal timing
12.5. ARM940T SDOUTBS to TDO relationship
12.6. ARM940T nTRST to RSTCLKBS relationship
12.7. ARM940T JTAG output signal
12.8. ARM940T JTAG input signal timing
12.9. ARM940T FCLK related debug output timings
12.10. ARM940T BCLK related debug output timings
12.11. ARM940T TCK related debug output timings
12.12. nTRST to DBGRQI relationship
12.13. ARM940T EDBGRQ to DBGRQI relationship
12.14. ARM940T DBGEN to Output relationship

List of Tables

2.1. CP15 register map
2.2. Register 0
2.3. CP15 register 1
2.4. Clocking modes
2.5. Cacheable bits register format 
2.6. CP15 register map 
2.7. Protection space register format
2.8. Permission encoding
2.9. CP15 data protection region registers
2.10. CP15 instruction protection region registers
2.11. CP15 protection region register format 
2.12. Area size encoding 
2.13. Cache operations through register 7
2.14. CP15 register 7 index/segment data format
2.15. CP15 Register 7 prefetch address format 
2.16. Programming the lockdown registers
2.17. Lockdown register format
2.18. CP15 register 15
3.1. Protection register format
3.2. Region size encoding  
4.1. CP15 Register 7 
4.2. Data write modes
6.1. BURST[1:0] encoding
7.1. Handshake encoding
8.1. Public instructions
8.2. ID code register
8.3. Scan chain number allocation
8.4. ARM940T EmbeddedICE register map
8.5. Watchpoint control register for data comparison
8.6. Watchpoint control register for data comparison bit functions
8.7. Watchpoint control register for instruction comparison
8.8. Watchpoint control register for instruction comparison bitfunctions
8.9. Debug control register
8.10. Debug status register
8.11. Vector catch register
8.12. Scan chain 15 format
8.13. Scan access mapping to CP15 register
8.14. Scan chain 4 and 5 addressing mode 
8.15. Scan chains 4 and 5 reading mode 
9.1. ARM940T in TrackingICE 
10.1. Scan chain 0 bit order
11.1. Symbols used in tables
11.2. Instruction cycle bus times
11.3. Data bus instruction times
12.1. ARM940T timing parameters
A.1. AMBA signals
A.2. Coprocessor interface signals
A.3. JTAG and TAP controller signals
A.4. Debug signals
A.5. Miscellaneous signals

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksof ARM Limited in the EU and other countries, except as otherwisestated below in this proprietary notice. Other brands and names mentionedherein may be the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

Where the term ARM is used it means “ARM or any of its subsidiariesas appropriate”.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A February1998 Technical amendments and reformatting
Revision B September1998 First full release.
Revision May2007 Converted for Infocenter
Copyright © 1998 ARM Limited. All rights reserved. DDI0092B
Non-Confidential