There are 11 possible interrupt sources. Access to the Smart
Card interrupts is made by the interrupt controller.
The latency of the RXREAD and TXTIDE interrupts are critical
to the performance of the cards, and ultimately limit the data rates
that can be supported. These two interrupts are accessed directly
by the interrupt controller.
The other nine sources are OR’ed together and presented as
a single interrupt source to the interrupt controller. The status
of these nine sources is stored in the SMINTSTAT register.
A bit is set due to a positive transition on the corresponding
raw interrupt source. Reading the SMINTSTAT register does not modify
its contents. For SMINSTAT[8:0], the interrupt is cleared by writing
a ‘1’ to the respective SMINTSTAT bit position. Writing a ‘0’ to
any position has no effect. SMINSTAT[10:9] are dynamically modified by
operations on the respective FIFOs.
Table 4.13. Interrupt sources
| SMINTSTAT bit | Name | Function |
|---|
| 0 | CARDIN | Smart card inserted |
| 1 | CARDOUT | Smart card removed |
| 2 | CARDUP | Smart card is powered up (activated) |
| 3 | CARDDN | Smart card is powered down (deactivated) |
| 4 | TXERR | Character transmission error |
| 5 | ATRSTOUT | ATR start timed out |
| 6 | ATRDTOUT | ATR duration timed out |
| 7 | BLKTOUT | Between block timed out |
| 8 | CHTOUT | Between character timed out |
| 9 | TXTIDE | Transmit FIFO tide mark reached |
| 10 | RXREAD | Read from receive FIFO required |
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