AMBA Smart Card Interface Data Sheet 4.2. Summary of Smart Card Interface Registers

4.2. Summary of Smart Card Interface Registers

All registers are read/write unless otherwise stated. None of the registers contains reserved bits (which would require read/modify/write to change the register contents).

If an n‑bit wide Smart Card register is read into an ARM register, bits 31 down to n of the ARM register are undefined.

The following registers are provided:

Table 4.1. Smart Card Interface register summary

Offset	Type	Width	Reset Value	Name	Description
`0x00 – 0x3C`	R/W	10/8	`0x000`	SMDATA	Data read or written from the interface.
`0x40`	R/W	2	`0x0`	SMCONV	Convention configuration register.
`0x44`	R/W	4	`0x0`	SMPARITY	Controls parity sense and handshaking.
`0x48`	R/W	3	`0x0`	SMTXRETRY	Number of retransmit attempts for T0 protocol.
`0x4C`	R/W	3	`0x0`	SMRXRETRY	Number of receive attempts for T0 protocol.
`0x50`	R/W	4	`0x0`	SMTXTIDE	Transmit FIFO tide level.
`0x54`	R/W	4	`0x0`	SMTXCOUNT	Transmit FIFO character count / flush Transmit FIFO.
`0x58`	R/W	4	`0x0`	SMRXTIDE	Receive FIFO tide level.
`0x5C`	R/W	4	`0x0`	SMRXCOUNT	Receive FIFO character count / flush Receive FIFO.
`0x60`	R/W	16	`0x0000`	SMRXTIME	Receive FIFO timeout value.
`0x64`	R/W	7	`0x00`	SMTCTRL	Terminal control register.
`0x68`	R/W	8	`0x00`	SMSTABLE	Debounce time value.
`0x6C`	W	3	`0x0`	SMICTRL	Activation, warm reset and deactivation card control register.
`0x70`	R/W	4/3	`0x0`	SMISTAT	Card detection, power and clock status.
`0x74`	R/W	16	`x0000`	SMATIME	Timer value for activation events (Smart Card clock cycles).
`0x78`	R/W	16	`0x0000`	SMDTIME	Timer value for deactivation events (etus).
`0x7C`	R/W	16	`0x0000`	SMATRSTIME	Maximum time between reset de-assertion and Start of ATR reception.
`0x80`	R/W	16	`0x0000`	SMATRDTIME	Maximum time duration from start to completion of ATR reception.
`0x84`	R/W	16	`0x0000`	SMBLKTIME	Maximum time between blocks.
`0x88`	R/W	16	`0x0000`	SMCHTIME	Maximum time between characters.
`0x8C`	R/W	8	`0x00`	SMCLKICC	Reference clock divisor value to provide the Smart Card clock frequency.
`0x90`	R/W	16	`0x0000`	SMNBAUD	Reference clock divisor value to provide the baud rate clock frequency.
`0x94`	R/W	8	`0x00`	SMNVALUE	Number of baud rate clock cycles that constitute an elementary time unit (etu).
`0x98`	R/W	8	`0x00`	SMCHGUARD	Extra guard time to provide the minimum time between characters (etus).
`0x9C`	R/W	8	`0x00`	SMBKGUARD	Extra guard time to provide the minimum time between blocks (etus).
`0xA0`	R/W	2	`0x0`	SMSYNCTRL	Synchronous Smart Card control.
`0xA4`	R/W	4	`0x0`	SMSYNCDAT	Synchronous Smart Card data.
`0xA8`	R	2	`0x0`	SMRAWSTAT	Raw Smart Card I/O and clock status.
`0xAC`	R/W	11/9	`0x200`	SMINTSTAT	Interrupt status register

Copyright © 1997 ARM Limited. All rights reserved.	DDI 0095A
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