| SMCONV | 0x0 | The convention register is set to direct convention
for reading the initial character (TS) of the ATR. There are only
two valid TS values, 0x3B for direct or 0x3F for inverse convention.
The software will read the TS value and program the SMCONV accordingly. |
| SMPARITY | 0x0 | Even parity, character receive/transmit handshaking
disabled. Note: Character retry does not apply during the ATR sequence. |
| SMTCTRL | 0x01 | The interface must be put into receive mode.
Interrupts must be enabled as the card recognition, activation sequences
etc. are interrupt driven. |
| SMSTABLE | 0x64 | For a 48MHz (21ns) reference clock, the stable
(debounce) time is in terms of multiples of 1.38ms (0xFFFF x 21ns).
An initial value of 138ms is proposed. |
| SMATIME | 0xAFC8 | The SMATIME register must be programmed to
between 40000 and 45000 (0xAFC8) Smart Card clock cycles to satisfy the
minimum cold and warm reset RST low time requirements. |
| SMDTIME | 0x2710 | The SMDTIME is in terms of reference clock
periods. It times the three stages of the deactivation sequence.
The total time of the deactivation sequence must not take longer
than 1ms to complete. An initial value of 10000 (0x2710) periods
is suggested which is equivalent to an SMDTIME of approximately
0.21ms for a 48MHz (21ns) reference clock. This gives a total deactivation
time of approximately 0.65ms. |
| SMATRSTIME | 0x9C40 | The SMATRSTIME is in terms of Smart Card clock
cycles. After de-assertion of the reset RST signal, the start of
ATR sequence must occur within 40,000 (0x9C40) Smart Card clock
cycles. |
| SMATRDTIME | 0x4B00 | The SMATRDTIME is in terms of etus (elementary
time units, see Data Transfer ).
The complete ATR character sequence must be received within 19200
(0x4B00) etus. |
| SMCHTIME | 0x2580 | The SMCHTIME is in terms of etus and is the
maximum interval between the leading edges of two consecutive characters.
In the case of the ATR sequence, this is 9600 (0x2580) etus. It
also is applicable to characters in the transaction data stream
and is T=0 or T=1 mode dependent. |
| SMRXTIDE | 0x0 | This is the receive FIFO tide level. Although
a value of zero is proposed, any value between 0x0 and 0x7 can be
used. With a value of zero, the RXREAD interrupt is generated when
the initial TS character is loaded into the receive FIFO. |
| SMCLKICC | 0x17 | The SMCLKICC value is used to divide down the
reference clock to provide the Smart Card clock. The final Smart
Card clock frequency should be within the range 1–5MHz. For a 48MHz
reference clock, SMCLKICC should be programmed with a value of 23
(0x17) to provide an initial 1MHz Smart Card clock frequency. |
| SMNBAUD | 0x174 | An SMNBAUD value of 372 (0x174) is required
for a 1MHz Smart Card clock frequency, which is the initial proposed frequency
prior to ATR reception. Refer to Data Transfer . |
| SMNVALUE | 0x10 | Please refer to Data Transfer . An SMNVALUE value of 16 (0x10) is required
for a 1 MHz Smart Card clock frequency, which is the initial proposed
frequency prior to ATR reception. |
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