AMBA Smart Card Interface Data Sheet

Table of Contents

1. Introduction
1.1. Conformance
1.2. Smart Card Overview
1.3. Features
2. Signal Description
2.1. ASB Signals
2.2. Internal Signals
2.3. External Signals
3. Functional Description
3.1. Block Diagram
3.2. Overview of Smart Card Operation
3.2.1. ASB Interface
3.2.2. Interface Reset
3.2.3. Interface Configuration
3.2.4. Card Detection
3.2.5. Card Activation Sequence
3.2.6. Warm Reset Sequence
3.2.7. (ATR) Answer-To-Reset Sequence
3.2.8. Data Transaction
3.2.9. Card Deactivation Sequence
3.2.10. Data Transfer
3.2.11. Example Configurations
3.3. Character Framing
3.3.1. EMV Character Timing For T=0 (Character Protocol)
3.3.2. EMV Character Timing For T=1 (Block Protocol)
3.3.3. Transmit
3.3.4. Receive
3.3.5. Block time and time between characters
3.3.6. Parity error
3.3.7. RXREAD interrupt
4. Programmer’s Model
4.1. Introduction
4.2. Summary of Smart Card Interface Registers
4.3. Register Descriptions
4.3.1. SMDATA: Data register [10/8] (+0x00 – 0x3C)
4.3.2. SMCONV: Convention configuration register [2] (+0x40)
4.3.3. SMPARITY: Parity control [4] (+ 0x44)
4.3.4. SMTXRETRY: Transmit retry limit [3] (+0x48)
4.3.5. SMRXRETRY: Receive retry limit [3] (+0x4C)
4.3.6. SMTXTIDE: Transmit FIFO tide mark [4] (+0x50)
4.3.7. SMTXCOUNT: Transmit FIFO count (R) / Flush (W) [4] (+0x54)
4.3.8. SMRXTIDE: Receive FIFO tide mark [4] (+0x58)
4.3.9. SMRXCOUNT: Receive FIFO count (R) / flush (W) [4] (+0x5C)
4.3.10. SMRXTIME: Receive/Read timeout [16] (+0x60)
4.3.11. SMTCTRL: Terminal control [7] (+0x64)
4.3.12. SMSTABLE: Debounce timer [8] (+0x68)
4.3.13. SMICTRL: ICC control (write only) [3] (+0x6C)
4.3.14. SMISTAT: ICC status [4] (+0x70)
4.3.15. SMATIME: Activation event timing [16] (+0x74)
4.3.16. SMDTIME: Deactivation event timing [16] (+0x78)
4.3.17. SMATRSTIME: Time to Start of ATR reception [16] (+0x7C)
4.3.18. SMATRDTIME: Maximum Duration of the ATR character stream [16] (+0x80)
4.3.19. SMBLKTIME: Receive timeout [16] (+0x84)
4.3.20. SMCHTIME: Character To Character timeout [16] (+0x088)
4.3.21. SMCLKICC: External Smart Card clock frequency [8] (+0x8C)
4.3.22. SMNBAUD: Baud rate clock [16] (+0x90)
4.3.23. SMNVALUE: SMNBAUD cycles [8] (+0x94)
4.3.24. SMCHGUARD: Character To Character Extra Guard Time [8] (+0x098)
4.3.25. SMBKGUARD: Block Guard Time [8] (+0x09C)
4.3.26. SMSYNCTRL: Asynchronous/Synchronous Multiplexing Control [2] (+0xA0)
4.3.27. SMSYNCDAT: Synchronous Smart Card data [4] (+0xA4)
4.3.28. SMRAWSTAT: Raw I/O and clock status (read only) [2] (+0A8)
4.3.29. SMINTSTAT: Interrupt status (read/write) [11/9] (+0AC)
4.4. Interrupts
A. Test Registers
A.1. Test Registers
A.1.1. SMTESTCTRL: Test control register [9] (+0xB0)
A.1.2. SMACTTIME: Activation timer status (read only) [16] (+0xB4)
A.1.3. SMDATATIME: Data timer status (read only) [16] (+0xB8)
A.1.4. SMNBAUDCOUNT: Baud counter status (read only) [16] (+0xBC)
A.1.5. SMNVALUECOUNT: Value counter status (read only) [8] (+0xC0)
A.1.6. SMRXTIMESTAT: Rx timer status (read only) [16] (+0xC4)
A.1.7. SMTXRXSTATUS: TxRx status (read only) [8] (+0xC8)
A.1.8. SMINPUTCTRL: Primary Inputs Test Register [5] (+0xCC)
A.1.9. SMOUTPUTSTAT: Primary Outputs Test Register [10] (+0xD0)
A.1.10. SMSTBLCOUNT: Debounce (stable) Timer Status [8] (+0xD4)
A.1.11. SMSTATESTATE: Activation/Deactivation and TxRx State Machines Status [17] (+0xD8)
A.1.12. SMCLOCKCOUNT: Smart card clock divider status register [8] (+0xDC)
A.1.13. SMSTBCLOCK: Strobe clock generation register (read only) [0] (+0xFC)

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Revision History
Revision ANovember 1997First release
Copyright © 1997 ARM Limited. All rights reserved.DDI 0095A