4.3. Register descriptions

The following registers are provided at offsets from a base address decoded to drive the PSEL input:

KBDCR (MSECR)

Control register

KBDSTAT (MSESTAT)

Status register

KBDDATA (MSEDATA)

Transmit/receive data register

KBDCLKDIV (MSECLKDIV)

Clock division register

There are additional test registers described in Appendix A Test Harness.

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