3.2. Overview of the Keyboard/Mouse Interface Operation

The Keyboard interface generates two interrupts:


indicates that the transmit buffer is empty and that another byte can be transmitted.


indicates that a byte has been received by the interface.

The keyboard interface is held in reset until the enable bit in the KBDCR control register is set. The interface can be controlled on the basis of the interrupts generated, or by polling the status flags in the control register. The TX interrupt is generated when the transmit buffer has been emptied and the interface is ready to be programmed with another character for transmission. The RX interrupt is set when a complete character has been received in the receive buffer, and the byte is ready to be read from the register. The received data parity bit, RXP, is available in the control register. Odd parity is used. The keyboard and mouse interface state machines are clocked at a frequency of 8MHz, derived from the RefClk input. A frequency just less than 8MHz should also allow the block to operate properly.

The KbClkIn signal is sampled by a internal 1MHz clock, which is derived from the 8MHz internal clock, to reduce the effects of noise and metastability.

In a typical configuration, KbdClkIn and KbdDataIn are connected to open drain I/O pads with pull-up resistors, for example KCLK and KDATA at the peripheral interface. These are controlled by their respective KbdClkEn and KbdDataEn signals.

The external clock signal is always driven by the keyboard device, except when the host system wants to prevent transmission by the keyboard.

When the interface has been enabled, it awaits one of two possible events:

If simultaneous transmission and reception occur, the keyboard device is inhibited from sending its data until transmission is complete.

If the transmit register is written during reception, the transmission from the interface is delayed until reception from the keyboard device has completed.

If the transmit register is written while the receive register is full, the transmission from the interface occurs and it is possible for the receive register to be read during this transmission.

Transmission and reception timeouts of 64μs and 16ms are applied respectively, though no timeout interrupts are generated.

The timing requirements of the interface are shown in Figure 3.2: Keyboard/mouse controller receive protocol.

Figure 3.2. Keyboard/mouse controller receive protocol

The timing requirements of the interface are shown in Figure 3.3: Keyboard/mouse timing and controller request to send protocol.

Figure 3.3. Keyboard/mouse timing and controller request to send protocol

Table 3.1: Keyboard/mouse interface timings shows the normal timings for the interface signals.

Table 3.1. Keyboard/mouse interface timings

TkclkKeyboard clock period1 100μs 
TkckIKeyboard clock LOW time0.5 50μs 
TkckhKeyboard clock HIGH time0.5 50μs 
TdsiSetup on KDATA to KCLK falling for Receive1 Tkckh - 1μsμs1
TdhiHold on KDATA from KCLK rising for Receive1 Tkckh - 1μsμs1
TdsoSetup on KDATA to KCLK rising for TransmitTkckl - 1μs Tkckl 1
TdhoHold on KDATA from KCLK falling for Transmit0ns 1μs 1
TkiTime for which KCLK is held LOW to request a send63.56464.5μs1
TkrgKCLK LOW from controller to KCLK LOW from peripheral for request to send1  μs1
TksbKCLK LOW to KDATA LOW hold time for request to send1  μs1, 2


  • The KDATA and KCLK signals in the diagrams and tables in this section relate to the respective external pad connections.

  • The KDATA will proceed the KCLK in this implementation, so the value for Tksb shown on the diagram above is negative, that is, safe.

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