A.2.1. KBDTEST1 [7] (+0x20)

This write-only register provides control over the clocks source to the block for test purposes.

Table A.2. KBDTEST1 register details


Clear the Divide by 8 counter

Writing a one to this location generates a pulse to reset the divide by 8 counter.


Register Div8 Clock (1MHz)

Used in test mode as a source for the 1MHz synchronizing clock signal, by successive write to the location.


Clock Select Lines


Normal operation. The input 8MHz is selected and the Div8 (1MHz) clock is generated from the 8MHz clock.


PSEL ANDed with PSTB is driven as the internal 8MHz clock. This means that when this clock source is selected, every access to the block generates a positive clock pulse internally. The Div8 clock is generated from this internal 8MHz clock in this mode, ie. the pulsed clock.


The MC and RC1 bits are used as the clock sources for the 8MHz and 1MHz clocks respectively. To generate an internal clock transition, program these bits with the last written values inverted (in other words, write 0 and then 1 creates a LOW to HIGH transition and vice versa).

2T2When 1, the output of the timer prescaler is connected to KBDCR bit[2] (RXP) allowing its LOW time of 16μs +/- 7 μs to be checked.
1T1When set to 1, this bit allows the timeout section of the timer (the last 8 bits) to be clocked at 8 times the normal prescaler output rate.
0T0This bit allows the middle section of the timer (for timing 64μs) to be clocked by the 8MHz input directly, rather than from the prescaler output.
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