5.1. Test Registers

Extra registers are provided inside the Generic Infra Red Interface for test purposes only and should not be accessed during normal mode of operation. They are memory mapped as follows:

Table 5.1. Test registers

Address OffsetTypeWidthReset ValueNameDescription
0x20R/W160x0000GIRTCRGeneric IR Test Control Register
0x24R160x0000GIRTTXCDGeneric IR Test Transmit Current Clock Divider Value
0x28R160x0000GIRTRXCDGeneric IR Test Receive Current Clock Divider Value
Copyright © 1998 ARM Limited. All rights reserved.ARM DDI 0097A
Non-Confidential