1.8.4. Horizontal Back Porch (HBP)

The 8-bit Horizontal Back Porch (HBP) field is used to specify the number of dummy pixel clocks to insert at the beginning of each line or row of pixels. After the line clock for the previous line has been negated, the value in HBP is used to count the number of pixel clocks to wait before starting to output the first set of pixels in the next line. HBP generates a wait period ranging from 0–255 pixel clock cycles (program to value required minus one).

Note

The pixel clock pin LcdCP, does not transition during these dummy pixel clock cycles in passive display mode (pixel clock transitions continuously in active display mode).

Table 1.10 shows the location of the four bit-fields located in LCD Timing 0 Register (LcdTiming0). The LCD controller must be disabled (LcdEn=0) when changing the state of any field within this register. The reset state of all bitfields is unknown and must be initialized before enabling the LCD.

Figure 1.16. LCD Timing 0 Register (LcdTiming0)

Table 1.10. LCD Timing 0 Register (LcdTiming0)

BitNameDescription
9-0PPLPixels-per-lineEncoded value (from 1–1024) used to specify number of pixels contained within each lineon the LCD display
15-10HSWHorizontal Sync Pulse WidthEncoded value (from 0–63) used to specify number of pixel clock periods to pulse the lineclock at the end of each line.Note that pixel clock is held in its inactive state during the generation of the line clock inpassive display mode, and is permitted to transition in active display mode.
23-16HFPHorizontal Front PorchEncoded value (from 0–255) used to specify number of pixel clock periods to add to the endof a line transmission before line clock is asserted.Note that pixel clock is held in its inactive state during the end of line wait period in passivedisplay mode, and is permitted to transition in active display mode.
31-24HBPHorizontal Back PorchEncoded value (from 0–255) used to specify number of pixel clock periods to add to thebeginning of a line transmission before the first set of pixels is output to the display.Note that pixel clock is held in its inactive state during the beginning of line wait period inpassive display mode, and is permitted to transition in active display mode.
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